In recent years, an effort has been undertaken to improve a resolution performance on semiconductor wafers (hereinafter, simply referred to as wafer) so as to develop more advanced semiconductor devices with a continuous attempt for a finer design (circuit pattern) size and RET (Resolution Enhancement Technique). Therefore, photomasks also have introduced finer design rules, higher integration, more complex OPC (Optical Proximity Correction), etc. of circuit patterns (size) to be formed, making photomask manufacturing more difficult. It is because, in addition to that finer circuit pattern sizes improve the degree of integration of circuit patterns for increasing the number of circuit patterns within a photomask layout (the number of figures), adoption of advanced RET such as highly precise OPC, an auxiliary pattern, etc. increases the complexity of the circuit patterns.
Generally, when the difficulty of manufacturing (hereinafter, referred to as manufacturing difficulty level) is high, a manufacturing cost will be increased, and the price of photomasks will be raised in the case of manufacturing photomasks. Among all other semiconductor devices, the production of SoC (System on Chip) products in small lot and a large number of products has a proportion of the photomask cost to the profit higher than that of memory products, thus resulting in higher total order cost of the photomask; therefore, cost management of photomask is very important. To reduce the cost of photomask, photomask manufacturers' efforts to lower the cost and cooperation of ordering parties of the photomask are essential. The photomask manufacturers have improved manufacturing yields and optimized manufacturing processes for higher efficiency, and the ordering parties of the photomasks have studied and introduced optimization of specifications of photomask such as size specification and defect specification, and introduction of effective and rational pass/fail determination methods of photomasks.